The present invention relates generally to charge pumps for boosting voltages in microelectronic circuitry, and particularly to a charge pump stage architecture with body effect minimization.
Non-volatile memory arrays, such as erasable, programmable read only memory (EPROM) or flash memory arrays, or electrically erasable, programmable read only memory (EEPROM) arrays, require high positive or negative voltages to program and erase memory cells of the array. Typically, these voltages are higher than the voltage supplied (Vdd). Charge pumps are generally used to boost on-chip voltages above the supply voltage Vdd to reach the voltages required for program or erasing.
A charge pump typically comprises cascaded stages that progressively boost the voltage to higher levels. The charge pump functions by progressively storing more charge on a capacitor which is part of a capacitor-diode combination, with several such stages being placed together in a network to obtain the desired increase in voltage. The diode functions to prevent discharge of the capacitor prior to placing the additional charge thereon.
Reference is now made to FIGS. 1A and 1B, which illustrate a commonly used charge pump architecture, called a four-phased-clock, threshold-voltage-canceling pump architecture, for a four-stage charge pump (see Umezawa, IEEE Journal of Solid State Circuits Vol. 27, 1992, page 1540). FIG. 1A illustrates two stages of the charge pump in greater detail than FIG. 1B, which illustrates four stages of the charge pump.
The charge pump circuit includes a plurality of charge transfer transistors (reference letters m1) connected in series. In FIG. 1B, four such charge transfer transistors are shown, labeled m1, m2, m3 and m4. Charge transfer transistors m1 may use, but are not limited to, CMOS (complementary metal oxide semiconductor) technology, being either n-channel or p-channel (NMOS or PMOS) field effect transistors (FETs). (As explained further hereinbelow, NMOS is generally used to pump positive voltages, whereas PMOS is generally used to pump negative voltages.) The MOSFETs have a control electrode (gate, labeled g), a first electrode (drain, labeled d) and a second electrode (source, labeled s), connected to nodes, as described hereinbelow. (Since MOSFETs are typically symmetrical components, the true designation of xe2x80x9csourcexe2x80x9d and xe2x80x9cdrainxe2x80x9d is only possible once a voltage is impressed on the terminals of the transistors. The designations of source and drain throughout the specification should be interpreted, therefore, in the broadest sense.) Preferably, the bulks (labeled b) of the charge transfer transistors m1 are coupled to a reference line (shown as REF in FIG. 1A, but omitted for the sake of simplicity in FIG. 1B) for receiving a reference voltage, generally ground in the case of NMOS.
FIGS. 1A and 1B illustrate a positive charge pump based on NMOS. The source of charge transfer transistor m1 is connected to node n0, which is connected to Vdd. The gate of charge transfer transistor m1 is connected to node g1, and the drain is connected to node n1. The source of charge transfer transistor m2 is connected to node n1, the gate is connected to node g2, and the drain is connected to node n2. Similarly, as shown in FIG. 1B, the source of charge transfer transistor m3 is connected to node n2, the gate to node g3, and the drain to node n3. Likewise, the source of charge transfer transistor m4 is connected to node n3, the gate to node g4, and the drain to nodes.
Two-phase, non-overlapping pulse trains PH1 and PH2 are provided, such as from a pulse generator (not shown). By non-overlapping it is meant that 0 to 1, and 1 to 0 voltage transitions of one pulse never overlap with the transitions of the other pulse. The PH1 and PH2 phases inject energy into the pump through large capacitors 5 into nodes ni. Accordingly, in the illustrated embodiment, a large capacitor 5 is connected from pulse train PH1 to node n1, and another large capacitor 5 is connected from pulse train PH1 to node n3. Another large capacitor 5 is connected from pulse train PH2 to node n2, and another large capacitor 5 is corrected from pulse train PH2 to node n4. The charge is transferred along the pump through charge transfer transistors mi connecting node n1 to node n1+l.
Similarly, two-phase, non-overlapping pulse trains PH1A and PH2A are also provided. The PH1A and PH2A phases inject energy into the pump through small capacitors 11 into nodes gi. Capacitors 11 preferably have a much smaller capacitance than large capacitors 5. In the illustrated embodiment, a small capacitor 11 is connected from pulse train PH1A to node g2, and another small capacitor 11 is connected from pulse train PH1A to node g4. Another small capacitor 11 is connected from pulse train PH2A to node g1, and another small capacitor 11 is connected from pulse train PH2A to node g3.
As seen in FIGS. 1A and 1B, a plurality of auxiliary transistors t1 (ie., t1, t2, t3 and t4) are provided. Each auxiliary transistor t1 has its drain connected to the gate node g1 of each charge transfer transistor mi (i.e. m1, m2, m3 and m4, respectively). The source of each auxiliary transistor ti is connected to the source of each charge transfer transistor m1 (i.e., node nixe2x88x921). The gate of each auxiliary transistor ti is connected to the drain of each charge transfer transistor mi (i.e., node ni) The bulk of each auxiliary transistor ti is connected to the bulk of each charge transfer transistor mi, which is generally grounded. The auxiliary transistors ti and the PH1A and PH2A phases control the gate voltage of the charge transfer transistors mi.
The operation of the first stage of the pump is now explained, with all subsequent stages operating in the same manner. The operation commences with the PH1 phase starting to rise. Initially, charge transfer transistors m1 and m2 are non-conducting (i.e., turned off), since the PH1A and PH2A phases are in their low phase. The PH1 phase then fully rises and injects energy into node n1, raising (or xe2x80x9cpushingxe2x80x9d) node n1 to a voltage boosted above Vdd, such as 2 Vdd. The rise of node n1 forces node g1 to Vdd through auxiliary transistor t1. Since the source of charge transfer transistor m1 is connected to Vdd at node n0, the gate-source voltage bias Vgs of charge transfer transistor m1 is zero, assuring that transistor m1 is turned off.
After a short time, typically in the order of several nanoseconds, the PH1A phase rises, which makes charge transfer transistor m2 conduct (i.e., turns on). During this the, node n1 is at a higher voltage than node n2. Since, as just mentioned, charge transfer transistor m2 is conducting, charge is transferred from node n1 to node n2. During the next phase, the PH2 phase rises and the PH1 phase drops. This causes node n1 to drop and node n2 to rise, thereby causing charge to be transferred from node n2 to node n3. In this manner charge is transferred along the pump. Each of the gi nodes is raised by a Vdd level with respect to the ni nodes when charge transfer is taking place. In the latter stages of the pump, the source and drain nodes (i.e., nodes n3 and n4) are raised well above the bulk, which is usually grounded.
The large voltage difference between the high source/drain voltages and the low bulk voltage causes a problem, called the body or bulk effect, which is now explained. (The terms body and bulk are used interchangeably throughout the specification and claims)
Positive charge pumps generally use NMOS transistors, and this requires the body of the charge transfer transistors to be at the lowest voltage, in general ground (GND). (Negative charge pumps have the opposite requirement, and PMOS transistors are generally used.) However, in positive charge pumps there can be a significant loss of energy in the latter pump stages due to the xe2x80x9cbody effectxe2x80x9d. In NMOS, the body effect is an increase in the threshold voltage (Vt), due to the fact that the bulk or body of the transistor is at a lower voltage than the source. Due to the body effect, the threshold voltage V1 of the NMOS transistors progressively increases from the stages near the input terminal of the charge pump to the stages near the output terminal. For example, in the prior art charge pump of FIG. 1, the threshold voltage V1 of charge transfer transistors mi progressively increases from transistor m1 to transistor m4. In transistor m4, as mentioned hereinabove, the source and drain nodes n3 and n4, have been raised well above the bulk. This reduces the efficiency of the charge pump, because the voltage gain of each stage decreases, which means that a higher number of stages is necessary for generating a given voltage.
In some CMOS processes, such as triple-well and silicon-on-insulator (SOI), it is possible to raise the bulk of the NMOS charge transfer transistors above the grounded substrate, which would reduce the body effect by diminishing the voltage difference between the bulk and the source/drain. However, in the prior art, this entails certain risks. For example, if the bulk voltage is raised above the source or drain voltage, then parasitic bipolar transistors (typically used in CMOS circuitry) can turn on, which can cause either latchup or drain the charge from the pump.
In many circuits, not necessarily charge pumps, the bulk effect is eliminated by connecting the bulk node to the source node. This is not possible in a charge pump, however, because the xe2x80x9csourcexe2x80x9d can be higher or lower than the xe2x80x9cdrainxe2x80x9d by Vdd, depending upon the clock cycle. This would cause parasitic diodes to turn on, resulting in the unwanted bipolar transistor turn-on and latchup.
One method for compensating for the body effect is described in U.S. Pat. No. 6,064,251 to Park. Park uses charge pump stages coupled in series. Each charge pump stage has two clock terminals that receive two phase shifted clock signals. The charge pump stages are configured so that adjacent charge pump stages receive different clock signals. The phases of the clock signals are such that the pump elements are boosted well above the threshold voltage Vt, thereby providing the transistors with sufficient overdrive to transfer energy along the pump. However, clock boosting uses a significant amount of power consumption and is thus very wasteful.
The present invention provides a novel charge pump stage for pumping high positive voltages, which minimizes the aforementioned body effect.
In the present invention, an NMOS transistor, preferably configured as a source follower, raises the bulk voltage of a charge pump stage to a level below or equal to the minimum of the source and drain voltage of the charge transfer transistor at that stage. In one embodiment, for triple-well technology, the body effect is reduced by raising P-wells of the NMOS transistors to a level below or equal to the minimum of the source/drain voltages of the entire clock cycle. This limits the increase of the threshold voltages (Vt) of the transistors at high voltage, which significantly improves pumping efficiency. At no point is the bulk voltage higher than the source/drain voltage.
There is thus provided in accordance with a preferred embodiment of the present invention a method for operating a charge pump, the method including biasing a bulk voltage of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.
In accordance with a preferred embodiment of the present invention the bulk voltage of the charge pump stage is raised to a level below a minimum of source/drain voltages of a charge transfer transistor at that stage.
Further in accordance with a preferred embodiment of the present invention a bulk voltage of a present charge pump stage is raised by using an output of a previous charge pump stage as an input to a gate of a source follower transistor to drive the bulk voltage of the present charge pump stage.
Still further in accordance with a preferred embodiment of the present invention an output of the source follower transistor is lower than an input of the source follower transistor by a threshold voltage Vt.
In accordance with a preferred embodiment of the present invention the charge pump stage employs triple-well transistors.
Further in accordance with a preferred embodiment of the present invention voltages of P-wells of the transistors are raised to a level not greater than the minimum of the source and drain voltages of the transistors.
In accordance with a preferred embodiment of the present invention the transistors include NMOS (n-channel metal oxide semiconductor) transistors.
There is also provided in accordance with a preferred embodiment of the present invention a charge pump including a plurality of positive charge pump stages, each stage including at least one NMOS charge transfer transistor, wherein a bulk voltage of the at least one charge transfer transistor is raised to a level not greater than a minimum of a voltage level of a source and a drain of the at least one charge transfer transistor in that charge pump stage.
In accordance with a preferred embodiment of the present invention there is also provided a circuit that drives the bulk voltages.
Further in accordance with a preferred embodiment of the present invention an input to a previous charge pump stage is used as an input to the circuit that drives the bulk of the present charge pump stage.
Still further in accordance with a preferred embodiment of the present invention the circuit includes a transistor configured as a source follower.
Additionally in accordance with a preferred embodiment of the present invention the circuit includes at least one of a comparator, a level shifter, all operative amplifier (OP-AMP), and an inverting stage.
In accordance with a preferred embodiment of the present invention, at at least one of the charge pump stages, a gate of the source follower is driven by an input voltage and a source of the source follower drives the bulk.
Further in accordance with a preferred embodiment of the present invention the input to a previous charge pump stage is applied to the gate of the source follower of the present charge pump stage.
Still further in accordance with a preferred embodiment of the present invention the source of the source follower drives the bulk of all transistors in the present charge pump stage.
Additionally in accordance with a preferred embodiment of the present invention the bias on the gate of the source follower is an available voltage.
There is also provided in accordance with a preferred embodiment of the present invention a charge pump including a plurality of positive charge pump stages each stage including at least one NMOS charge transfer transistor, wherein a bulk voltage of at least one of the charge pump stages is biased so as to reduce body effect without forward biasing diodes of that at least one charge pump stage.
In accordance with a preferred embodiment of the present invention a bull voltage of at least one of the charge transfer transistors is raised to a level not greater in a minimum of a voltage level of a source and a drain of the at least one charge transfer transistor in that charge pump stage.
There is also provided in accordance with a preferred embodiment of the present invention a charge pump including at least one positive charge pump stage including at least one NMOS charge transfer transistor m1, which includes a control terminal and first, second and third terminals, wherein the control terminal of the at least one charge transfer transistor mi is connected to a node gi, the first terminal of the at least one charge transfer transistor mi is connected to a node nixe2x88x921, the second terminal of the at least one charge transfer transistor mi is connected to a node ni, at least one source follower si including a control terminal and first, second and third terminals, wherein the control terminal of the at least one source follower si is driven by a first voltage, the first and third terminals of the at least one source follower si are connected through nodes pi and qi to the third terminal of the at least one charge transfer transistor mi, and the second terminal of the at least one source follower si is connected to a second voltage, at least one first pulse train adapted to inject energy into the pump via a first capacitor into node ni, at least one second pulse train adapted to inject energy into the pump via a second capacitor into node gi, at least one auxiliary transistor t1 including a control terminal and first, second and third terminals, wherein the second terminal of the at least one auxiliary transistor t1 is connected to the control terminal of the at least one charge transfer transistor mi, the first terminal of the at least one auxiliary transistor ti is connected to the first terminal of the at least one charge transfer transistor mi, the control terminal of the at least one auxiliary transistor t1 is connected to the second terminal of the at least one charge transfer transistor m1, and the third terminal of the at least one auxiliary transistor t1 is connected to the third terminal of the at least one charge transfer transistor mi.
In accordance with a preferred embodiment of the present invention, for i greater than 2, the control terminal of the at least one source follower si is driven by an input voltage from a previous stage the input voltage being the input to the charge transfer transistor mixe2x88x922 at the nixe2x88x923 node.
Further in accordance with a preferred embodiment of the present invention, for i greater than 2, the control terminal of the at least one source follower s1 is driven by an input voltage from a previous stage, the input voltage being the input to the charge transfer transistor mixe2x88x921 at a node previous to the nixe2x88x922 node.
Still further in accordance with a preferred embodiment of the present invention the second voltage is at node gi.
In accordance with a preferred embodiment of the present invention the second voltage is at an output of the charge pump stage.
Further in accordance with a preferred embodiment of the present invention the second voltage is at an output or input of the charge pump.
In accordance with a preferred embodiment of the present invention the control terminal includes a gate of the transistor, the first terminal includes a source of the transistor the second terminal includes a drain of the transistor, and the third terminal includes a bulk of the transistor.